LPT-port register overview:
DATA-register [BASE + 0]: D7 D6 D5 D4 D3 D2 D1 D0
Write:Write data to the output latch of the LPT-port.
The physical data lines of the LPT-port are updated according to the contents of the latch.
Read :in SPP mode: Read data from the output latch, NOT the actual states of de LPT-port data lines.
in EPP mode: if PCD bit in CONTROL-register is set, data is read from the LPT-port data lines;
otherwise, the output latch is read.
STATUS-register [BASE + 1]: 7 6 5 4 3 2 1 0
0:Time-out; set to '1' if timeout occured
1:?
2:?
3:LPT pin 15 [ERROR(-)]; bit is '1' if pin is HIGH
4:LPT pin 13 [SLCT IN]; bit is '1' if pin is HIGH
5:LPT pin 12 [PE]; bit is '1' if pin is HIGH *
6:LPT pin 10 [ACK(-)]; bit is '1' if pin is HIGH
7:LPT pin 11 [BUSY]; bit is '1' if pin is LOW
* An IRQ occures when this bit becomes set and bit 4 in CONTROL-register is set.
CONTROL-register [BASE + 2]: 7 6 5 4 3 2 1 0
0:LPT pin 1 [STROBE(-)]; pin is set LOW if bit is set to '1'
1:LPT pin 14 [AUTOFD(-)]; pin is set LOW if bit is set to '1'
2:LPT pin 16 [INIT(-)]; pin is set HIGH if bit is set to '1'
3:LPT pin 17 [SLCT(-)]; pin is set LOW if bit is set to '1'
4:IRQ Enable; if set to '1', assertion of ACK causes an interrupt (IRQ7)
5:PCDif set to '0', data lines are OUTPUT and data can be written;
if set to '1', data lines are INPUT and data can be read *
6:?
7:?
* Port must be in EPP mode for this function to work correctly.
CONFIG-register [BASE + 402h]: 7 6 5 4 3 2 1 0
0:FIFO empty; set to '1' if FIFO buffer is empty
1:FIFO full; set to '1' if FIFO buffer is full
2:?
3:?
4:?
7 6 5
0 0 0 SPP
0 0 1 Byte
0 1 0 Fast Centronics
0 1 1 ECP
1 0 0 EPP
1 0 1 Reserved
1 1 0 Test
1 1 1 Config